Chip multi processors (CMP) refer to implementing multiple processor units (CPU) in one chip. Each CPU may also be called a core. The cores in the CMP share certain resources among each other and may execute different processes concurrently. Sometimes, procedures executed by the cores of the CMP need to share and synchronize data among each other, so the hardware structure of the CMP must support inter-core communications. Currently, there are two types of mainstream inter-core communication mechanisms. One type is a bus-shared cache structure. The other type is a hardware message queue structure.
The bus-shared cache structure refers to that each core has a shared level-two or level-three cache for storing commonly used data, and consistency of data among the cores is ensured through a bus connecting the cores. Communications among the cores may be implemented through a shared data segment.
The hardware message queue structure refers to implementing a group of queues for each core in a manner of hardware. The operation of queues, as compared with the bus-shared cache structure, improves the efficiency of inter-core communications.
A high efficient inter-core communication mechanism is an important guarantee for high performance of the CMP. However, inter-core hardware message queue structures of the CMP in the prior art cannot satisfy inter-core message exchange and task scheduling with higher performance.